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1 1 mx25u8033e datasheet mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
2 2 contents features ................................................................................................................................................................. 5 t able 1. additional feature comparison ........................................................................................................... 7 pin configurations ............................................................................................................................................ 8 pin description ..................................................................................................................................................... 8 block diagram ...................................................................................................................................................... 9 da ta protection ................................................................................................................................................. 10 table 2. protected area sizes ......................................................................................................................... 11 table 3. 4k-bit secured otp defnition ........................................................................................................... 11 memory organization .............................................................................................................................................. 12 table 4. memory organization ....................................................................................................................... 12 device operation ............................................................................................................................................... 13 figure 1. serial modes supported............ .......................................................................................................13 hold feature ....................................................................................................................................................... 14 figure 2. hold condition operation ................................................................................................................ 14 command description ...................................................................................................................................... 15 table 5. command set .................................................................................................................................... 15 (1) write enable (wren) ................................................................................................................................ 17 (2) write disable (wrdi) ............ ..................................................................................................................... 17 (3) read identifcation (rdid) ......................................................................................................................... 17 (4) read status register (rdsr) ........... ........................................................................................................ 17 program/ erase flow with read array data....................................................................................................18 program/ erase flow without read array data (read p_fail/e_fail fag) .................................................... 19 wrsr flow ..................................................................................................................................................... 20 (5) write status register (wrsr) ............ ....................................................................................................... 22 table 7. protection modes ............................................................................................................................... 22 (6) read data bytes (read) .......................................................................................................................... 23 (7) read data bytes at higher speed (fast_read) .................................................................................... 23 (8) dual read mode (dread) ........................................................................................................................ 23 (9) 2 x i/o read mode (2read) ........... .......................................................................................................... 24 (10) 4 x i/o read mode (4read) ................................................................................................................... 24 (11) performance enhance mode ................................................................................................................... 25 (12) sector erase (se) .................................................................................................................................... 25 (13) block erase (be32k) ............................................................................................................................... 26 (14) block erase (be)......................................................................................................................................26 (15) chip erase (ce) ....................................................................................................................................... 26 (16) page program (pp)..................................................................................................................................27 (17) 4 x i/o page program (4pp) .................................................................................................................... 27 (18) deep power-down (dp) ........................................................................................................................... 27 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
3 3 (19) release from deep power-down (rdp), read electronic signature (res) ........................................... 28 (20) read electronic manufacturer id & device id (rems), (rems2), (rems4) ........... .............................. 28 table 8. id defnitions .................................................................................................................................... 29 (21) enter secured otp (enso) .................................................................................................................... 29 (22) exit secured otp (exso) ....................................................................................................................... 29 (23) read security register (rdscur) ......................................................................................................... 29 table 9. security register defnition ............................................................................................................... 30 (24) write security register (wrscur) ......................................................................................................... 30 (25) write protection selection (wpsel) ........................................................................................................ 30 figure 3. wpsel flow ........... ........................................................................................................................ 31 (26) single block lock/unlock protection (sblk/sbulk) ............ .................................................................. 32 figure 4. block lock flow ............................................................................................................................... 32 figure 5. block unlock flow ............................................................................................................................ 33 (27) read block lock status (rdblock) ...................................................................................................... 34 (28) gang block lock/unlock (gblk/gbulk)................................................................................................34 (29) read sfdp mode (rdsfdp) ............ ...................................................................................................... 35 figure 6. read serial flash discoverable parameter (rdsfdp) sequence..................................................35 table 10. signature and parameter identifcation data values ............ .......................................................... 36 table 11. parameter table (0): jedec flash parameter tables.....................................................................37 table 12. parameter table (1): macronix flash parameter tables ................................................................. 39 power-on state .................................................................................................................................................. 41 electrical specifications ............................................................................................................................. 42 absolute maximum ratings .................................................................................................................. 42 figure 7. maximum negative overshoot waveform ....................................................................................... 42 capacitance ta = 25c, f = 1.0 mhz .......................................................................................................... 42 figure 8. maximum positive overshoot waveform ........... .............................................................................. 42 figure 9. input test waveforms and measurement level ............ ............................................... 43 figure 10. output loading ........... ........................................................................................................... 43 table 13. dc characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) ........................... 44 table 14. ac characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) .......................... 45 timing analysis ....................................................................................................................................................... 46 figure 11. serial input timing .......................................................................................................................... 46 figure 12. output timing ................................................................................................................................. 46 figure 13. hold timing ........... ......................................................................................................................... 47 figure 14. wp# setup timing and hold timing during wrsr when srwd=1 ............ .................................. 47 figure 15. write enable (wren) sequence (command 06) ............ .............................................................. 47 figure 16. write disable (wrdi) sequence (command 04) ............ ............................................................... 48 figure 17. read identifcation (rdid) sequence (command 9f) .................................................................. 48 figure 18. read status register (rdsr) sequence (command 05) ........... ................................................. 48 figure 19. write status register (wrsr) sequence (command 01) ............ ................................................ 49 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
4 4 figure 20. read data bytes (read) sequence (command 03) (50mhz).....................................................49 figure 21. read at higher speed (fast_read) sequence (command 0b) ........... ................................... 50 figure 22. dual read mode sequence (command 3b)..................................................................................50 figure 23. 2 x i/o read mode sequence (command bb) .............................................................................. 51 figure 24. 4 x i/o read mode sequence (command eb) ............................................................................ 51 figure 25. 2 x i/o read enhance performance mode sequence (command bb) ......................................... 52 figure 26. 4 x i/o read enhance performance mode sequence (command eb) ......................................... 53 figure 27. page program (pp) sequence (command 02) ............................................................................54 figure 28. 4 x i/o page program (4pp) sequence (command 38) ............ ................................................... 54 figure 29. sector erase (se) sequence (command 20) ............................................................................... 55 figure 30. block erase 32kb (be32k) sequence (command 52) ................................................................ 55 figure 31. block erase (be) sequence (command d8) ................................................................................ 55 figure 32. chip erase (ce) sequence (command 60 or c7) ........................................................................ 55 figure 33. deep power-down (dp) sequence (command b9)......................................................................56 figure 34. release from deep power-down and read electronic signature (res) sequence (command ab) 56 figure 35. release from deep power-down (rdp) sequence (command ab) ............................................ 57 figure 36. read electronic manufacturer & device id (rems) sequence (command 90/ef/df) ............... 57 figure 37. read security register (rdscur) sequence (command 2b) ..................................................... 58 figure 38. write security register (wrscur) sequence (command 2f) .................................................... 58 figure 39. power-up timing ............................................................................................................................ 59 table 15. power-up timing and vwi threshold ............................................................................................. 59 initial delivery state ..............................................................................................................................59 operating conditions ...................................................................................................................................... 60 figure 40. ac timing at device power-up ...................................................................................................... 60 figure 41. power-down sequence ................................................................................................................. 61 erase and programming performance ................................................................................................... 62 latch-up characteristics ............................................................................................................................. 62 ordering informa tion ..................................................................................................................................... 63 part name description .................................................................................................................................... 64 package information ....................................................................................................................................... 65 revision history ................................................................................................................................................ 69 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
5 5 8m-bit [x 1/x 2/x 4] 1.8v cmos mxsmio ? (serial multi i/o) flash memory features general ? single power supply operation - 1.65 to 2.0 volt for read, erase, and program operations ? serial peripheral interface compatible -- mode 0 and mode 3 ? 8m: 8,388,608 x 1 bit structure or 4,194,304 x 2 bits (two i/o read mode) structure or 2,097,152 x 4 bits (four i/o read mode) structure ? 256 equal sectors with 4k byte each - any sector can be erased individually ? 32 equal blocks with 32k byte each - any block can be erased individually ? 16 equal blocks with 64k byte each - any block can be erased individually ? program capability - byte base - page base (256 bytes) ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast read - 1 i/o: 80mhz with 8 dummy cycles - 2 i/o: 80mhz with 4 dummy cycles, equivalent to 160mhz - 4 i/o: 70mhz with 6 dummy cycles, equivalent to 280mhz; - fast program time: 1.2ms(typ.) and 3.0ms(max.)/page (256-byte per page) - byte program time: 10us (typ.) - fast erase time - 30ms(typ.) and 200ms(max.)/sector (4k-byte per sector) - 200ms(typ.) and 1000ms(max.)/block (32k-byte per block) - 500ms(typ.) and 2000ms(max.)/block (64k-byte per block) - 5.0s(typ.) and 10s(max.)/chip ? low power consumption - low active read current: 12ma(max.) at 80mhz, 7ma(max.) at 33mhz - low active erase/programming current: 25ma (max.) - low standby current: 8ua (typ.)/30ua (max.) ? low deep power down current: 8ua(max.) ? t ypical 100,000 erase/program cycles ? 20 years data retention softw are features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defnes the size of the area to be software protection against program and erase instruc - tions - additional 4k-bit secured otp for unique identifer ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector or block - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst). mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
6 6 ? status register feature ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems, rems2 and rems4 commands for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameter (sfdp) mode hardw are features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? hold#/sio3 - hold feature, to pause the device without deselecting the device or serial data input/output for 4 x i/o read mode ? p ackage - 8-land uson (4x4mm) - 8-pin sop (150mil) - 8-pin sop (200mil) - 8-land wson (6x5mm) - all devices are rohs compliant and halogen-free general description the mx25u8033e is 8,388,608 bit serial flash memory, which is confgured as 1,048,576 x 8 internally. the mx25u8033e features a serial peripheral interface and software protocol allowing operation on a simple 4-wire bus while it is in single i/o mode. the four bus signals are a clock input (sclk), a serial data input (si), a serial data output (so) and a chip select (cs#). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits input and data output. when it is in four i/o read mode, the si pin, so pin, wp# pin and hold# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the mx25u8033e mxsmio ? (serial multi i/o) provides sequential read operation on the whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the specifed page or sector/block locations will be executed. program command is executed on byte basis, or page (256 bytes) basis. erase command is executed on 4k-byte sector, 32k-byte block, or 64k-byte block, or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via the wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode. the mx25u8033e utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
7 7 table 1. additional feature comparison additional features part name protection and security read performance identifer flexible block protection (bp0-bp3) individual protect 4k-bit secured otp 2 i/o read 4 i/o read res (command: ab hex) rems/ rems2/ rems4 (command: 90/ef/df hex) rdid (command: 9f hex) mx25u8033e v v v v v 34 (hex) c2 34 (hex) (if add=0) c2 25 34 (hex) mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
8 8 pin configurations pin description 8-land uson (4x4mm) 8-pin sop (150mil/200mil) symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 hardware write protection: connect to gnd or serial data input & output (for 4xi/o read mode) hold#/sio3 to pause the device without deselecting the device or serial data input & output (for 4xi/o read mode) vcc + 1.8v power supply gnd ground 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc hold#/sio3 sclk si/sio0 8 7 6 5 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc hold#/sio3 sclk si/sio0 8-land wson (6x5mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc hold#/sio3 sclk si/sio0 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
9 9 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 hold#/sio3 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
10 10 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or pro- gramming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register ar - chitecture of the device constrains that the memory contents can only be changed after specifc command sequenc - es have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? v alid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? w rite enable (wren) command: wren command is required to set the write enable latch bit (wel) before is - suing other commands to change data. the wel bit will return to resetting stage while the following conditions occurred: - power-up - completion of w rite disable (wrdi) command - completion of w rite status register (wrsr) command - completion of page program (pp) command - completion of quad page program (4pp) command - completion of sector erase (se) command - completion of block erase 32kb (be32k) command - completion of block erase (be) command - completion of chip erase (ce) command - completion of w rite protection select (wpsel) command - completion of w rite security register (wrscur) command - completion of single block lock/unlock (sblk/sbulk) command - completion of gang block lock/unlock (gblk/gbulk) command ? deep power down mode: by entering deep power down mode, the fas h device also is under protected from writ- ing all commands except release from deep power down mode command (rdp) and read electronic signature command (res). ? advanced security features: there are some protection and security features which protect content from inad - vertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as table of " protected area sizes ", the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. please refer to table of " protected area sizes ". - the hardware protected mode (hpm) use wp#/sio2 to protect the (bp3, bp2, bp1, bp0) bits and srwd bit. if the system goes into four i/o read mode, the feature of hpm will be disabled. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
11 11 table 2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 8mb 0 0 0 0 0 (none) 0 0 0 1 1 (1block, protected block 15th) 0 0 1 0 2 (2blocks, protected block 14th~15th) 0 0 1 1 3 (4blocks, protected block 12nd~15th) 0 1 0 0 4 (8blocks, protected block 8th~15th) 0 1 0 1 5 (16blocks, protected all) 0 1 1 0 6 (16blocks, protected all) 0 1 1 1 7 (16blocks, protected all) 1 0 0 0 8 (16blocks, protected all) 1 0 0 1 9 (16blocks, protected all) 1 0 1 0 10 (16blocks, protected all) 1 0 1 1 11 (8blocks, protected block 0th~7th) 1 1 0 0 12 (12blocks, protected block 0th~11st) 1 1 0 1 13 (14blocks, protected block 0th~13rd) 1 1 1 0 14 (15blocks, protected block 0th~14th) 1 1 1 1 15 (16blocks, protected all) table 3. 4k-bit secured otp defnition ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting de - vice unique serial number - which may be set by factory or system maker. please refer to table 3. 4k-bit se - cured otp defnition. - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enso command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exso command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) command to set customer lock-down bit1 as "1". please refer to table of "security register defnition" for security register bit defnition and table of "4k-bit secured otp defnition" for address range defnition. note: once lock-down whatever by factory or customer, it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
12 12 memory organization table 4. memory organization block (64kb) block (32kb) sector (4kb) address range 15 31 | 30 255 0ff000h 0fffffh individual sector lock/unlock : : : 240 0f0000h 0f0fffh 14 29 | 28 239 0ef000h 0effffh individual block lock/unlock : : : 224 0e0000h 0e0fffh 13 27 | 26 223 0df000h 0dffffh : : : 208 0d0000h 0d0fffh 12 25 | 24 207 0cf000h 0cffffh : : : 192 0c0000h 0c0fffh 11 23 | 22 191 0bf000h 0bffffh : : : 176 0b0000h 0b0fffh 10 21 | 20 175 0af000h 0affffh : : : 160 0a0000h 0a0fffh 9 19 | 18 159 09f000h 09ffffh : : : 144 090000h 090fffh 8 17 | 16 143 08f000h 08ffffh : : : 128 080000h 080fffh 7 15 | 14 127 07f000h 07ffffh : : : 112 070000h 070fffh 6 13 | 12 111 06f000h 06ffffh : : : 96 060000h 060fffh 5 11 | 10 95 05f000h 05ffffh : : : 80 050000h 050fffh 4 9 | 8 79 04f000h 04ffffh : : : 64 040000h 040fffh 3 7 | 6 63 03f000h 03ffffh : : : 48 030000h 030fffh 2 5 | 4 47 02f000h 02ffffh : : : 32 020000h 020fffh 1 3 | 2 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 1 | 0 15 00f000h 00ffffh individual sector lock/unlock : : : 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
13 13 device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this device, it enters standby mode and remains in the standby mode until next cs# falling edge. in standby mode, so pin of the device is high-z. 3. when correct command is inputted to this device, it becomes active mode and remains in the active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data is shifted out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 1. "serial modes supported" . 5. for the following instructions: rdid, rdsr, rdscur, read, fast_read, 2read, dread, 4read, res, rems, rems2, rems4 and rdsfdp, the shifted-in instruction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be32k, be, ce, pp, 4pp, rdp, dp, wpsel, sblk, sbulk, gblk, gbulk,enso, exso, and wrscur, the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. while a w rite status register, program or erase operation is in progress, to the memory array is neglected and while not affect the current operation of wrscur, wpsel write status register, program and erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
14 14 hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select (cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until se- rial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 2. figure 2. hold condition operation hold# cs# sclk hold condition (standard) hold condition (non-standard) the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
15 15 command description table 5. command set command (byte) wren (write enable) wrdi (write disable) rdsr (read status register) wrsr (write status register) se (sector erase) be 32k (block erase 32kb) be (block erase 64kb) 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 20 (hex) 52 (hex) d8 (hex) 2nd byte values ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to write new values of the status register to erase the selected sector to erase the selected 32kb block to erase the selected block command (byte) ce (chip erase) pp (page program) 4pp (quad page program) dp (deep power down) rdp (release from deep power down) 1st byte 60 or c7 (hex) 02 (hex) 38 (hex) b9 (hex) ab (hex) 2nd byte ad1 ad1 3rd byte ad2 ad2 4th byte ad3 ad3 action to erase whole chip to program the selected page quad input to program the selected page enters deep power down mode release from deep power down mode read commands i/o 1 1 1 2 2 4 command (byte) read (normal read) fast read (fast read data) rdsfdp (read sfdp) 2read (2 x i/o read command) dread (1i / 2o read command) 4read (4 x i/o read command) clock rate (mhz) 50 80 80 80 80 70 1st byte 03 (hex) 0b (hex) 5a (hex) bb (hex) 3b (hex) eb (hex) 2nd byte ad1 ad1 ad1 ad1 ad1 ad1 3rd byte ad2 ad2 ad2 ad2 ad2 ad2 4th byte ad3 ad3 ad3 ad3 ad3 ad3 5th byte dummy dummy dummy dummy dummy action n bytes read out until cs# goes high n bytes read out until cs# goes high read sfdp mode n bytes read out by 2 x i/o until cs# goes high n bytes read out by 4 x i/o until cs# goes high program/erase commands mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
16 16 note 1: add=00h will output the manufacturer id frst and add=01h will output device id frst. 2: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hidden mode. command (byte) rdid (read identifc- ation) res (read electronic id) rems (read electronic manufacturer & device id) rems2 (read id for 2x i/o mode) rems4 (read id for 4x i/o mode) enso (enter secured otp) exso (exit secured otp) 1st byte 9f (hex) ab (hex) 90 (hex) ef (hex) df (hex) b1 (hex) c1 (hex) 2nd byte x x x x 3rd byte x x x x 4th byte x add add add action outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out 1-byte device id output the manufacturer id & device id output the manufacturer id & device id output the manufacturer id & device id to enter the 4k-bit secured otp mode to exit the 4k-bit secured otp mode command (byte) rdscur (read security register) wrscur (write security register) sblk (single block lock sbulk (single block unlock) rdblock (block protect read) gblk (gang block lock) gbulk (gang block unlock) 1st byte 2b (hex) 2f (hex) 36 (hex) 39 (hex) 3c (hex) 7e (hex) 98 (hex) 2nd byte ad1 ad1 ad1 3rd byte ad2 ad2 ad2 4th byte ad3 ad3 ad3 action to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) individual block (64k-byte) or sector (4k-byte) write protect individual block (64k-byte) or sector (4k-byte) unprotect read individual block or sector write protect status whole chip write protect whole chip unprotect security/id/mode setting/reset commands command (byte) wpsel (write protect selection) 1st byte 68 (hex) 2nd byte 3rd byte 4th byte action to enter and enable individal block protect mode mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
17 17 (1) write enable (wren) the write enable (wren) instruction is to set write enable latch (wel) bit. for those instructions like pp, 4pp, se, be32k, be, ce, wpsel, wrscur, sblk, sbulk, gblk, gbulk and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. (please refer to figure 15 ) (2) write disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. (please refer to figure 16 ) the wel bit will be reset while the following conditions occurred: - power-up - completion of w rite disable (wrdi) instruction - completion of w rite status register (wrsr) instruction - completion of page prog ram (pp) instruction - completion of quad pag e program (4pp) instruction - completion of sector erase (se) instruction - completion of block eras e 32kb (be32k) instruction - completion of block eras e (be) instruction - completion of chip eras e (ce) instruction - completion of w rite protection select (wpsel) instruction - completion of w rite security register (wrscur) instruction - completion of single blo ck lock/unlock (sblk/sbulk) instruction - completion of gang bloc k lock/unlock (gblk/gbulk) instruction (3) read identifcation (rdid) the rdid instruction is to read the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id is c2(hex), the memory type id is 25(hex) as the frst-byte device id, and the individual device id of second-byte id are listed as table of "id defnitions". (please refer to table 8 ) the sequence of issuing rdid instruction is: cs# goes low sending rdid instruction code24-bits id data out on so to end rdid operation can drive cs# to high at any time during data out. (please refer to figure 17 ) while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on the cycle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/wpsel/wrscur/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
18 18 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wren=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdslock to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. (please refer to figure 18 ) for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: program/ erase flow with read array data mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
19 19 program/ erase flow without read array data (read p_fail/e_fail fag) wr en co mm and program /erase co mm and write progr am data/addres s (w ri te erase addre ss) rdsr command rdscur command program /er ase su ccessfully yes no progra m /erase fail yes start p_fail/e_fail=1 ? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wren=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdblock to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
20 20 wrsr flow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wren=1? no rds r command read w el=0, bp[3:0] , q e, and srwd data mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
21 21 table 6. status register note 1: see the table 2 "protected area size". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta- tus register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is ap - plied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/ erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrm to be 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in table 2) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be ex - ecuted. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default. which is un-protected. qe bit. the quad enable (qe) bit, non-volatile bit, while it is "0" (factory default), it performs non-quad and wp# is enable. while qe is "1", it performs quad i/o mode and wp# is disabled. in the other word, if the system goes into four i/o mode (qe=1), the features of hpm and hold will be disabled. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
22 22 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the pro - tected area of memory (as shown in table 2 ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on sics# goes high. (please refer to figure 19 ) the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 7. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in table 2 . as the above table showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when sr wd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when sr wd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software pro - tected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
23 23 hardware protected mode (hpm): - when sr wd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system enter quad i/o qe=1, the feature of hpm will be disabled. (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 3-byte address on si data out on soto end read operation can use cs# to high at any time during data out. (please refer to fig- ure 20) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_read operation can use cs# to high at any time during data out. (please refer to figure 21 ) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (8) dual read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the following data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte address on si 8-bit dummy cycle data out interleave on so1 & so0 to end dread operation can use cs# to high at any time during data out. (please refer to figure 22 ) mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
24 24 while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. (9) 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address inter - leave on sio1 & sio0 4 dummy cycles on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out (please refer to figure 23 for 2 x i/o read mode timing waveform). while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. (10) 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status reg - ister must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address af - ter each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address inter - leave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. (please refer to figure 24 ) while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
25 25 (11) performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. (please note figure 25 2xi/o read enhance performance mode sequence and figure 26 4xi/o read enhance performance mode se- quence) after entering enhance mode, following cs# go high, the device will stay in the read mode and treat cs# go low of the frst clock as address instead of command cycle. another sequence of issuing 2read (or 4read) instruction especially useful in random access is: cs# goes low sending 2read (or 4read) instruction 3-bytes address interleave on sio1, sio0 (sio3, sio2, sio1 & sio0) performance enhance toggling bit p[3:0] ( p[7:0] ) 2 (or 4) dummy cycles data out still cs# goes high cs# goes low (reduce 2read or 4read instruction) 24-bit random access address (please refer to figure 25 and figure 26 for 2x i/o and 4xi/o read enhance performance mode timing waveforms). in the 2xi/o performance-enhancing mode, p[3:2] must be toggling with p[1:0]; likewise p[3:0]=21h, 12h, 30h or 03h can make this mode continue and reduce the next 2read instruction. once p[3:2] is no longer toggling with p[1:0]; likewise p[3:0]=33h, 00h, 22h or 11h and afterwards cs# is raised and then lowered, the system then will es- cape from performance enhance mode and return to normal operation. in the 4xi/o performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; likewise p[7:0]=ffh,00h,aah or 55h and afterwards cs# is raised and then lowered, the system then will es - cape from performance enhance mode and return to normal operation. (12) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table of memory organization) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of the address been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. (please refer to figure 29) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the sector erase cycle is in progress. the wip sets during the tse timing, and clears when sector erase cycle is completed, and the write enable latch (wel) bit is cleared. if the sector is protected by bp3 ~ 0 (wpsel=0) or by individual lock (wpsel=1), the sector erase (se) instruction will not be executed on the sector. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
26 26 (13) block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see table of memory organiza - tion) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte address on sics# goes high. (please refer to figure 30) the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while he block erase cycle is in progress. the wip sets during the tbe32k timing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp3 ~ 0 (wpsel=0) or by individual lock (wpsel=1), the block erase (tbe32k) instruction will not be executed on the block. (14) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (please refer to table of memory organization) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the least signifcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. (please refer to figure 31 ) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the block erase cycle is in progress. the wip sets during the tbe timing, and clears when block erase cycle is completed, and the write enable latch (wel) bit is cleared. if the block is protected by bp3 ~ 0 (wpsel=0) or by individual lock (wpsel=1), the block erase (be) instruction will not be executed on the block. (15) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must be executed to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. (please refer to figure 32) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the chip erase cycle is in progress. the wip sets during the tce tim - ing, and clears when chip erase cycle is completed, and the write enable latch (wel) bit is cleared. if the chip is protected by bp3 ~ 0 (wpsel=0) or by individual lock (wpsel=1), the chip erase (ce) instruction will not be ex - ecuted. it will be only executed when bp3, bp2, bp1, bp0 all set to "0". mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
27 27 (16) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device pro - grams only the last 256 data bytes sent to the device. if the entire 256 data bytes are going to be programmed, a7- a0 (the eight least signifcant address bits) should be cleared. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. (please refer to figure 27 ) the cs# must be kept to low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be ex - ecuted. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked while the page program cycle is in progress. the wip sets during the tpp timing, and clears when page program cycle is completed, and the write enable latch (wel) bit is cleared. if the page is protected by bp3 ~ 0 (wpsel=0) or by individual lock (wpsel=1), the page program (pp) instruction will not be executed. (17) 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) in - struction must be executed to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" be - fore sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application of lower clock less than 70mhz. for system with faster clock, the quad page program cannot provide more actual favors, because the required internal page program time is far more than the time data fows in. therefore, we sug - gest that while executing this command (especially during sending data), user can slow the clock speed down to 70mhz below. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0]cs# goes high. (please refer to figure 28) if the page protected by bp3 ~ 0 (wpsel=0) or by individual lock (wpsel=1), the quad page program (4pp) instruction will not be executed. (18) deep power-down (dp) the deep power-down (dp) instruction is for setting the device to minimizing the power consumption, (the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruc - tion to enter, during the deep power-down mode, the device is not active and all write/program/erase instruction are ignored. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. (please refer to figure 33 ) mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
28 28 once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (those instructions allow the id being reading out). when power- down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. (19) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is completed by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 14 . ac characteristics. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions on next page. this is not the same as rdid instruction. it is not recommended to use for new design. for new design, please use rdid instruction. the sequence is shown as figure 34 and figure 35 . even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. (20) read electronic manufacturer id & device id (rems), (rems2), (rems4) the rems, rems2 and rems4 instruction provides both the jedec assigned manufacturer id and the specifc device id. the instruction is initiated by driving the cs# pin low and shift the instruction code "90h", "dfh" or "efh" followed by two dummy bytes and one bytes address (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 36. the device id values are listed in table of id defnitions. if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continu - ously, alternating from one to the other. the instruction is completed by driving cs# high. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
29 29 table 8. id defnitions command type mx25u8033e rdid (jedec id) manufacturer id memory type memory density c2 25 34 res electronic id 34 rems/rems2/rems4 manufacturer id device id c2 34 (21) enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. while device is in 4k-bit secured otp mode, main array access is not available. the additional 4k-bit secured otp is independent from main array, and may be used to store unique serial number for system identifer. after entering the secured otp mode, follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. please note that wrsr/wrscur/wpsel commands are not acceptable during the access of secure otp region, once security otp is lock down, only read related commands are valid. (22) exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. (23) read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. (please see figure 37 ) the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory-lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for cus - tomer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be updated any more. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
30 30 (24) write security register (wrscur) the wrscur instruction is for setting the values of security register bits. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the ldso bit is an otp bit. once the ldso bit is set, the value of ldso bit can not be altered any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. (please see figure 38 ) the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail reserved reserved reserved ldso (indicate if lock-down) secured otp indicator bit 0=normal wp mode 1=individual mode (default=0) 0=normal erase succeed 1=individual erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - - - 0 = not lock- down 1 = lock-down (cannot program/ erase otp) 0 = non- factory lock 1 = factory lock non-volatile bit (otp) volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit (otp) non-volatile bit (otp) table 9. security register defnition (25) write protection selection (wpsel) when the system accepts and executes wpsel instruction, bit 7 in the security register will be set. the wren (write enable) instruction is required before issuing wpsel instruction. it will activate sblk, sbulk, rdblock, gblk, gbulk etc instructions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block methods. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the individual block protect mode cs# goes high. every time after the system is powered-on the security register bit 7 is checked, if wpsel=1, then all the blocks and sectors will be write-protected by default. user may only unlock the blocks or sectors via sbulk and gbulk instructions. program or erase functions can only be operated after the unlock instruction is executed. once wpsel is set, it cannot be changed. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
31 31 figure 3. wpsel flow rdscur(2bh) command rdsr command rdscur(2bh) command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wren command wpsel=1? wpsel(68h) command wpsel enable. block protected by individual lock (sblk, sbulk, ? etc). wpsel instruction function fow is as follows: mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
32 32 figure 4. block lock flow rdscur(2bh) command start wren command sblk command ( 36h + 24bit address ) rdsr command rdblock command ( 3ch + 24bit address ) block lock successfully yes yes block lock fail no data = ffh ? wip=0? lock another block? block lock completed no yes no no yes wpsel=1? wpsel command (26) single block lock/unlock protection (sblk/sbulk) these instructions are only effective after wpsel was executed. the sblk instruction is for write protection a spec- ifed block (or sector) of memory, using a max -a16 or (a max -a12) address bits to assign a 64kbyte block (or 4k bytes sector) to be protected as read only. the sbulk instruction will cancel the block (or sector) write protection state. this feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (gbulk). the wren (write enable) instruction is required before issuing sblk/sbulk instruction. the sequence of issuing sblk/sbulk instruction is: cs# goes low send sblk/sbulk (36h/39h) instructionsend 3 address bytes assign one block (or sector) t o be protected on si pin cs# goes high. the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. sblk/sbulk instruction function fow is as follows: mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
33 33 figure 5. block unlock flow wren command rdscur(2bh) command sbulk command ( 39h + 24bit address ) rdsr command yes wip=0? unlock another block? yes no no yes unlock block completed? start wpsel=1? wpsel command mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
34 34 (27) read block lock status (rdblock) this instruction is only effective after wpsel was executed. the rdblock instruction is for reading the status of protection lock of a specifed block (or sector), using amax-a16 (or amax-a12) address bits to assign a 64k bytes block (4k bytes sector) and read protection lock status bit which the frst byte of read-out cycle. the status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. the status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (3ch) instruction send 3 address bytes to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. (28) gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is for enable/disable the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruction cs# goes high. the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
35 35 (29) read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a jedec standard, jesd216. figure 6. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
36 36 table 10. signature and parameter identifcation data values description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
37 37 table 11. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 1b b1h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 0b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 007fffffh (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 0000b 00h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 ffh ffh mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
38 38 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 1000b 08h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0100b 04h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b eeh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 0b unused 07:05 111b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 0000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0000b 00h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (4-4-4) fast read opcode 4bh 31:24 ffh ffh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
39 39 table 12. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 20h 00h 20h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 50h 16h 50h 16h h/w reset# pin 0=not support 1=support 65h:64h 00 0b 4ff6h h/w hold# pin 0=not support 1=support 01 1b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 0b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1111 1111b (ffh) program suspend/resume 0=not support 1=support 12 0b erase suspend/resume 0=not support 1=support 13 0b unused 14 1b wrap-around read mode 0=not support 1=support 15 0b wrap-around read mode opcode 66h 23:16 ffh ffh wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 ffh ffh individual block lock 0=not support 1=support 6bh:68h 00 1b c8d9h individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 0b individual block lock opcode 09:02 0011 0110b (36h) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 0b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
40 40 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: w ait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: all unused and undefned area data is blank ffh. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
41 41 power-on state the device is at the following states after power-up: - standby mode (please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage while the vcc reaches the following lev - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the fash device has no response to any command. for further protection on the device, after vcc reaching the vwi level, a tpuw time delay is required before the device is fully accessible for commands like write enable (wren), page program (pp), quad page program (4pp), sector erase (se), block erase 32kb (be32k), block erase (be), chip erase (ce), wrscur and write status regis - ter (wrsr). if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tpuw after vcc reached vwi level - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl, even time of tpuw has not passed. please refer to the fgure of "power-up timing". note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during this stage if a write, program, erase cycle is in progress. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
42 42 notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. absolute maximum ra tings electrical specifications capacitance ta = 25c, f = 1.0 mhz figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 2.5v 0v -1.0v 20ns vcc+1.0v 2.0v 20ns symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
43 43 figure 9. input test waveforms and measurement level figure 10. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +1.8v cl=30pf including jig capacitance mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
44 44 table 13. dc characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) note 1. typical values at vcc = 1.8v, t = 25 c. these currents are valid for all product versions (package and speeds). symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 8 30 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 2 8 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 12 ma f=80mhz, sclk=0.1vcc/0.9vcc, so=open 7 ma f=33mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 8 20 ma program status register in progress, cs#=vcc icc4 vcc sector/block (32k, 64k) erase current (se/be/be32k) 1 20 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
45 45 table 14. ac characteristics (temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v) symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be, ce, dp, res,rdp wren, wrdi, rdid, rdsr, wrsr d.c. 80 mhz frsclk fr clock frequency for read instructions 50 mhz ftsclk ft clock frequency for 2read instructions 80 mhz fq clock frequency for 4read instructions 70 mhz f4pp clock frequency for 4pp (quad page program) 70 mhz tch (1) tclh clock high time serial (fsclk) 6 ns normal read (frsclk) 9 ns 4pp (70mhz) 7 tcl (1) tcll clock low time serial (fsclk) 6 ns normal read (frsclk) 9 ns 4pp (70mhz) 7 tclch (2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl (2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 7 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 5 ns tshch cs# not active setup time (relative to sclk) 7 ns tshsl (3) tcsh cs# deselect time read 12 ns write/erase/program 30 ns tshqz (2) tdis output disable time 8 ns thlch hold# active setup time (relative to sclk) 4 ns tchhh hold# active hold time (relative to sclk) 4 ns thhch hold# not active setup time (relative to sclk) 4 ns tchhl hold# not active hold time (relative to sclk) 4 ns thhqx tlz hold# to output low-z 8 ns thlqz thz hold# to output high-z 8 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 8 ns loading: 15pf 6 ns tclqx tho output hold time 0 ns twhsl write protect setup time 20 ns tshwl write protect hold time 100 ns tdp (2) cs# high to deep power-down mode 10 us tres1 (2) cs# high to standby mode without electronic signature read 10 us tres2 (2) cs# high to standby mode with electronic signature read 10 us tw write status register cycle time 40 ms tbp byte-program 10 30 us tpp page program cycle time 1.2 3 ms tse sector erase cycle time 30 200 ms tbe32 block erase (32kb) cycle time 200 1000 ms tbe block erase (64kb) cycle time 500 2000 ms tce chip erase cycle time 5 10 s notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. v alue guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a wrsr instruction when sr wd is set at 1. 4. test condition is shown as "figure 9. input test waveforms and measurement level" , "figure 10. output loading" . mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
46 46 figure 11. serial input timing timing analysis figure 12. output timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
47 47 figure 13. hold timing tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# figure 14. wp# setup timing and hold timing during wrsr when srwd=1 high-z 01h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so figure 15. write enable (wren) sequence (command 06) 21 34567 high-z 0 06h command sclk si cs# so mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
48 48 figure 16. write disable (wrdi) sequence (command 04) 21 34567 high-z 0 04h command sclk si cs# so figure 17. read identifcation (rdid) sequence (command 9f) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh figure 18. read status register (rdsr) sequence (command 05) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
49 49 figure 19. write status register (wrsr) sequence (command 01) 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01h high-z command figure 20. read data bytes (read) sequence (command 03) (50mhz) sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03h high-z command mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
50 50 figure 21. read at higher speed (fast_read) sequence (command 0b) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 configurable dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command figure 22. dual read mode sequence (command 3b) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 30 31 32 39 40 41 43 44 45 42 3b d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 24 add cycle 8 dummy cycle a23 a22 a1 a0 data out 1 data out 2 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
51 51 figure 23. 2 x i/o read mode sequence (command bb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bbh address bit22, bit20, bit18...bit0 address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 8 bit instruction 12 bit address data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 2 dummy cycles data output p2 p0 p3 p1 performance enhance indicator (note) notes: 1. hi-impedance is inhibited for the two clock cycles. 2. p3p1 & p2p0 (t oggling) is inhibited. figure 24. 4 x i/o read mode sequence (command eb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles performance enhance indicator (note) data output notes: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (t oggling) is inhibited. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
52 52 figure 25. 2 x i/o read enhance performance mode sequence (command bb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 11 18 19 20 bbh address bit22, bit20, bit18...bit0 address bit22, bit20, bit18...bit0 address bit23, bit21, bit19...bit1 address bit23, bit21, bit19...bit1 21 22 23 24 25 26 27 8 bit instruction 12 bit address 12 bit address data bit6, bit4, bit2...bit0, bit6, bit4.... data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... data bit7, bit5, bit3...bit1, bit7, bit5.... 2 dummy cycles 2 dummy cycles data output p2 p0 p3 p1 performance enhance indicator (note) n+1 ........... ....... ........... n+12 n+15 .... n+17 sclk si/sio0 so/sio1 cs# p2 p0 p3 p1 performance enhance indicator (note) data output notes: 1. performance enhance mode, if p3p1 & p2p0 (t oggling), ex: 21h, 12h, 30h or 03h. performance enhance recommend to keep 1 or 0 in performance enhance indicator . 2. reset the performance enhance mode, if p3=p1 or p2=p0 (not toggling), ex: 33h, 00h, 22h or 11h. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
53 53 figure 26. 4 x i/o read enhance performance mode sequence (command eb) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 1210 11 13 14 ebh address bit20, bit16..bit0 address bit21, bit17..bit1 data bit4, bit0, bit4.... data bit5 bit1, bit5.... 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 23 n high impedance wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... high impedance nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 8 bit instruction 6 address cycles 4 dummy cycles data output p4 p0 p5 p1 p6 p2 p7 p3 performance enhance indicator (note) sclk si/sio0 so/sio1 cs# address bit20, bit16..bit0 address bit21, bit17..bit1 p4 p0 p5 p1 p6 p2 p7 p3 data bit4, bit0, bit4.... data bit5 bit1, bit5.... wp#/sio2 address bit22, bit18..bit2 data bit6 bit2, bit6.... nc/sio3 address bit23, bit19..bit3 data bit7 bit3, bit7.... 6 address cycles 4 dummy cycles performance enhance indicator (note) data output notes: 1. performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (t oggling), ex: a5h, 5ah, 0fh, f0h. performance enhance recommend to keep 1 or 0 in performance enhance indicator . 2. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0 (not toggling), ex: aah, 55h, 00h, ffh. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
54 54 figure 27. page program (pp) sequence (command 02) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command figure 28. 4 x i/o page program (4pp) sequence (command 38) 20 21 17 16 12 8 4 0 13 9 5 1 4 4 4 4 0 0 0 0 5 5 5 5 1 1 1 1 21 3456789 6 address cycle data byte 1 data byte 2 data byte 3 data byte 4 0 22 18 14 10 6 2 23 19 15 11 7 3 6 6 6 6 2 2 2 2 7 7 7 7 3 3 3 3 sclk cs# si/sio0 so/sio1 nc/sio3 wp#/sio2 38h command 10 11 12 13 14 15 16 17 18 19 20 21 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
55 55 figure 29. sector erase (se) sequence (command 20) 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20h command figure 30. block erase 32kb (be32k) sequence (command 52) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52h command figure 31. block erase (be) sequence (command d8) 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8h command figure 32. chip erase (ce) sequence (command 60 or c7) 21 34567 0 60h or c7h sclk si cs# command mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
56 56 figure 33. deep power-down (dp) sequence (command b9) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command figure 34. release from deep power-down and read electronic signature (res) sequence (command ab) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
57 57 figure 35. release from deep power-down (rdp) sequence (command ab) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so abh command note: add=00h will output the manufacturer's id frst and add=01h will output device id frst. figure 36. read electronic manufacturer & device id (rems) sequence (command 90/ef/df) 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90h high-z command mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
58 58 figure 37. read security register (rdscur) sequence (command 2b) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 security register out security register out high-z msb 7 6543210 msb 7 sclk si cs# so 2b figure 38. write security register (wrscur) sequence (command 2f) 21 34567 0 2f command sclk si cs# mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
59 59 figure 39. power-up timing note: vcc (max.) is 2.0v and vcc (min.) is 1.65v. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. these parameters are characterized only. table 15. power-up timing and vwi threshold v cc v cc (min) v wi reset state of the flash chip selection is not allowed program, erase and write commands are ignored tvsl tpuw time read command is allowed device is fully accessible v cc (max) symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low (vcc rise time) 300 us tpuw(1) time delay to write instruction 1 10 ms vwi(1) command inhibit voltage 1.0 1.4 v mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
60 60 operating conditions at device power-up and power-down ac timing illustrated in figure 40 and figure 41 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 40. ac timing at device power-up notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
61 61 figure 41. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
62 62 erase and programming performance note: 1. t ypical program and erase time assumes the following conditions: 25 c, 1.8v, and checkerboard pattern. 2. under worst conditions of 85 c and 1.65v . 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. data retention parameter condition min. max. unit data retention 55?c 20 years latch-up characteristics parameter min. typ. (1) max. (2) unit write status register cycle time 40 ms sector erase cycle time (4kb) 30 200 ms block erase cycle time (32kb) 200 1000 ms block erase cycle time (64kb) 500 2000 ms chip erase cycle time 5 10 s byte program time (via page program command) 10 30 us page program time 1.2 3 ms erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 1.8v, one pin at a time. mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
63 63 ordering information part no. clock (mhz) temperature package remark mx25u8033em1i-12g 80 -40 c~85 c 8-sop (150mil) mx25u8033ezui-12g 80 -40 c~85 c 8-uson (4x4mm) mx25u8033ezni-12g 80 -40 c~85 c 8-wson (6x5mm) mx25u8033em2i-12g 80 -40 c~85 c 8-sop (200mil) mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
64 64 part name description mx 25 u 12 m1 i g option: g: rohs compliant and halogen-free speed: 12: 80mhz temperature range: i: industrial (-40c to 85c) package: m1: 150mil 8-sop m2: 200mil 8-sop zu: uson zn: wson density & mode: 8033e: 8mb type: u: 1.8v device: 25: serial flash 8033e mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
65 65 package information mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
66 66 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
67 67 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
68 68 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
69 69 revision history rev. no. descriptions page date 1.0 1. added 200mil 8sop package solution p3,5,54,55,57 nov/09/201 1 2. modifed order information format p54 1.1 1. removed advanced information from p54 dec/27/2011 ordering information 1.2 1. added sfdp content p12,32~37,42 mar/20/2012 1.3 1. added dread function p13,15,23,37,38,50 apr/15/2013 2. modifed sfdp wording p35~40 1.4 1. modifed absolute maximum ratings table p42 nov/06/2013 2. updated parameters for dc characteristics. p5, 44 3. updated erase and programming performance. p5, 45, 62 mx25u8033e p/n: pm1718 rev. 1.4, nov. 06, 2013
70 macronix international co., ltd. reserves the right to change product and specifcations without notice. mx25u8033e except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2011~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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